1. Field of Invention
The present invention relates to test circuits and test method for power switches, and more particularly to on-chip test circuits and test method for testing on-chip power switches.
2. Description of Related Art
Low power electronic systems incorporating circuit elements are increasingly prevalent, as SOC (system on chip) is widely used in many portable devices, for example, personal digital assistants (PDAs), digital still camera (DSC) and other electronic appliances.
Due to the dramatic increase of application complexity of portable devices, they need to use advanced process, for example, 45 nm, to implement as many features as possible. As the process progresses, the leakage current of circuit devices, namely PMOS and NMOS, increases, rapidly. In most portable devices, they need to reduce the standby current to extend battery life. The standby mode power consumption is now determined by the quiescent “off-state” leakage current of PMOS and NMOS devices including the gate tunneling and drain-to-source leakage current.
Therefore, as the number of circuit devices increases, the percentage of standby power consumption due to the above-mentioned leakage is increasing, and is becoming the dominant portion of the total system standby power consumption.
The most popular architecture for reducing the standby current is Multi-Threshold Complementary Metal-Oxide Semiconductor (MTCMOS). This architecture adds a high-VT (high threshold voltage) PMOS header device or a high-VT NMOS footer device in series to a circuit which can be shut down to reduce leakage in standby mode. The MTCMOS architecture (or power switch) isolates the power supply rails of the circuit which can be shut down by using higher threshold voltage devices as power rail “header” and “footer” standby switching devices feeding common internal “virtual supply” rails. The use of higher threshold voltage devices decreases the off-state leakage and gate tunneling effects that otherwise increase power consumption when the repeaters are not switching.
In general, power switches may be designed as being on-chip or off-chip. As for off-chip power switches, the power switches may be tested before they are installed. However, there is no good test method to test on-chip power switches in CP (chip probe) or FT (final test) stage. Therefore, it needs a testing circuit and a testing method to test on-chip power switches.